NAND flash memories including a three-dimensional memory cell array have been recently developed. In the three-dimensional memory cell array, memory cells are arranged three-dimensionally. In this memory device, there is a case where a memory cell array is provided above a CMOS (Complementary Metal Oxide Semiconductor) circuit that controls the memory cell array. In this case, heat load is applied to the CMOS circuit or a contact plug in a heat treatment process when the memory cell array is formed, and adversely affects electrical characteristics of a CMOS or contact resistance. For example, boron that is used as impurities in a diffusion layer of a P-MOSFET (MOS Field Effect Transistor) causes a short channel effect when being diffused to a channel portion. Further, when boron in the diffusion layer is diffused to the contact plug, a metal material of the contact plug and boron react with each other, so that contact resistance is increased in some cases.